1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly to a semiconductor device for improving the characteristics of contact (via) resistance in the entire semiconductor device and to a fabrication method thereof.
2. Description of the Related Art
A typical semiconductor device will be described with reference to FIGS. 1A and 1B. FIG. 1A is a plan view depicting a part of a top face of a typical semiconductor device (a semiconductor chip). FIG. 1B is a cross-sectional view of FIG. 1A sectioned at the dashed line 1B to 1B.
As seen from FIG. 1A and FIG. 1B, a typical semiconductor device 100 includes a semiconductor substrate 112.
This semiconductor substrate 112 has a first face 112a and a second face 112b which faces the first face 112a. In the first face 112a side, an element 113, such as a transistor, is formed, and on the first face 112a, a first insulation film 114 is formed covering the element 113.
In the first insulation film 114, a contact hole 116 is formed, which reaches the element 113 through the first insulation film 114. This contact hole 116 is filled with a conductive material to form a buried contact 116a in the contact hole 116.
A first interconnect section 122 is electrically connected to a top face 116aa of the buried contact 116a. The first interconnect section 122 extends on a surface 114a of the first insulation film 114. A line length of the first interconnect section 122 has a relatively long length, and is, for example, within a range of 1 mm to 5 mm.
A second insulation film 130 is formed to cover the surface 114a of the first insulation film 114 and the first interconnect section 122.
In the second insulation film 130, a via hole 132 is formed which extends through the second insulation film 130 to reach a part of the first interconnect section 122. This via hole 132 is filled with a conductive material so as to form a buried via 132a. 
In this case, an area ratio of opening areas of the contact hole 116 and the via hole 132 with respect to a total surface area of the semiconductor device 100 is 2% or less. Merely one or two or the like via holes 132 are formed in the entire semiconductor device 100.
A second interconnect section 142 extends on a surface 130a of the second insulation film 130. The second interconnect section 142 is electrically connected to a top face 132aa of the buried via 132a. 
Now a cumulative resistance distribution of the buried contacts 116a and the buried vias 132a in the typical semiconductor device 100 having the above-mentioned configuration will be described with a reference to FIG. 2.
FIG. 2 is a graph depicting cumulative resistance distributions of a semiconductor device having the above-mentioned configuration. A line length of an interconnect is 1 mm. The ordinate represents cumulative resistance distributions (%) and the abscissa represents resistance values (Ω) of buried contacts or buried vias. A phantom line A in FIG. 2 represents a set of comparison data, which indicates measured values when the interconnects section 122 is not grounded. A phantom line B in FIG. 2 represents measured values in case buried contacts are formed and the interconnect section 122 is grounded thereby.
As seen from the phantom line A in FIG. 2, across thereof each of the resistance values is about 10Ω since the interconnect section 122 is not grounded, merely a little dispersion is observed in the resistance distribution.
As seen from the phantom line B in FIG. 2, a set of comparison data indicates that about 50% of the measured resistance values have respectively higher values, such as 50Ω, and the resistance distribution shows a larger dispersion.
Japanese Patent Kokai No. 2000-208703 discloses a configuration of a semiconductor device wherein when a potential dividing circuit is formed in which a plurality of resistance elements are arranged, dummy patterns of resistance elements are arranged outside of resistance elements located at both ends so that fabrication dispersion is avoided by making uniform a density of paths contained in an entire pattern.
Japanese Patent Kokai No. H06-085080 discloses a fabrication method of a semiconductor device for preventing a generation of contact defects due to a dispersion of an etching speed caused by an in-plane distribution density of contact holes in an etch back steps performed after filling contact holes with tungsten (W), wherein dummy contact holes, to which an interconnect is not connected, are opened near predetermined contact holes, both predetermined contact holes and dummy contact holes are filled with conductive material, and an etch back step is performed.
Such a problem has been encountered in a semiconductor device having buried contacts and buried vias of the above-mentioned configuration, that a buried contacts and buried vias have higher resistance so as to causes a drop in voltage and a path delay in a circuit operation, which adversely affects electric characteristics of the device.
Therefore a technology for providing a semiconductor device having a configuration is desired, which can stabilize a circuit operation by making contact (via) resistance distribution between layers of a semiconductor to be less-dispersed.